AN1016/1098 1/3 application note notes on using the st623xb/st628xb uart by 8-bit micro application team 1 avoiding a spurious interrupt during reset care must be taken if during reset, the reception rxd/pd4 line is stuck at zero. in this case, a high-to-low transition will be latched inside the uart cell due to the reset structure, even if no real falling edge occured on rxd/pd4 line. this active falling edge will be acknowledged by the uart cell as a valid receive start bit. 88 uart clocks ( 8 clocks per bit) are then needed to receive one burst of 11 bits (1 start bit + 8 bit data + 1 parity bit + 1 stop bit). the re- ceive interrupt flag rxrdy (bit7 of uart control register) is set to 1 after all 11 bits have been received and if enabled, a receive interrupt is generated. to avoid this early uart in- terrupt, enabling of the uart receive interrupt should only occur after a software delay se- quence insterted just after the reset jump instruction. the rxrdy flag must also be cleared before or when enabling uart receive interrupt for the first time. the length of the time delay depends on the selected operating baud rate (bit br2..br0 of uart control register). the following tables show the required timing with respect to the selected baud rate: br2 br1 br0 f osc division f osc =8mhz time delay required 0.00 0.00 0.00 6656 1200 9.6ms 0.00 0.00 1.00 3328 2400 4.8ms 0.00 1.00 0.00 1664 4800 2.4ms 0.00 1.00 1.00 832 9600 1.2ms 1.00 0.00 0.00 416 19200 600s 1.00 0.00 1.00 256 31200 400s 1.00 1.00 0.00 208 38400 300s 1.00 1.00 1.00 reserved reserved reserved br2 br1 br0 f osc division f osc =4mhz time delay required 0.00 0.00 0.00 6656 600 19.2ms 0.00 0.00 1.00 3328 1200 9.6ms 0.00 1.00 0.00 1664 2400 4.8ms 0.00 1.00 1.00 832 4800 2.4ms 1.00 0.00 0.00 416 9600 1.2ms 1.00 0.00 1.00 256 15600 740s 1.00 1.00 0.00 208 19200 600s 1.00 1.00 1.00 reserved reserved reserved 1
avoiding a spurious interrupt during reset 2/3 the following delay loop sequence is proposed : reset ldi uartcr, 0ch ; select the faster baud rate (uart control reg.) ldi count, 03h; for count = 01h, the tempo takes approximately call tempo; 100us. in this example, time out is for 300us ; at f osc = 8mhz start ldi uartcr, 30h; now clear rxrdy flag (bit7) and can enable ; uart interrupts ... ... tempo ld a, count; total temporisation: 62cyc*count + 8cyc + 8cyc jrz endtemp loop1 ldi x, 08h loop2 dec x; ex: need 62cyc for 100us at f osc = 8mhz jrnz loop2 dec count nop nop jrnz loop1 endtempret .org 0ffeh jp reset important notes: the configuration (br2=1, br1=1, br0=0) for a faster baud rate should be chosen after reset in order to use a short time delay. this early uart receive interrupt feature can be used to detect after reset if the rxd/pd4 line is low (stuck at '0') or not.
3/3 avoiding a spurious interrupt during reset "the present note which is for guidance only aims at providing customers with information regarding their products in order for them to save time. as a result, stmicroelectronics shall not be held liable for any direct, indirect or consequential damages with respect to any claims arising from the content of such a note and/or the use made by customers of the information contained herein in connexion with their products." information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 1998 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the neth erlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com
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